An important semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 100. Each cell 100 contains a storage capacitor 140 and an access field effect transistor or transfer device 120. For each cell, one side of storage capacitor 140 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of storage capacitor 140 is connected to the drain of transfer device 120. The gate of transfer device 120 is connected to a word line 180. The source of transfer device 120 is connected to a bit line 160 (also known in the art as a digit line). With the components of memory cell 100 connected in this manner, it is apparent that word line 180 controls access to storage capacitor 140 by allowing or preventing a signal (representing a logic “0” or a logic “1”) carried on bit line 160 to be written to or read from storage capacitor 140. Thus, each cell 100 contains one bit of data (i.e., a logic “0” or logic “1”).
FIG. 2 illustrates, in a block diagram, an architecture for a DRAM circuit 240. DRAM 240 contains a memory array 242, row and column decoders 244, 248 and a sense amplifier circuit 246. Memory array 242 consists of a plurality of memory cells 200 (constructed as illustrated in FIG. 1) whose word lines 280 and bit lines 260 are commonly arranged into rows and columns, respectively. Bit lines 260 of memory array 242 are connected to sense amplifier circuit 246, while its word lines 280 are connected to row decoder 244. Address and control signals are input into DRAM 240 on address/control lines 261. Address/control lines 261 are connected to column decoder 248, sense amplifier circuit 246, and row decoder 244, and are used to gain read and write access, among other things, to memory array 242.
Column decoder 248 is connected to sense amplifier circuit 246 via control and column select signals on column select lines 262. Sense amplifier circuit 246 receives input data destined for memory array 242 and outputs data read from memory array 242 over input/output (I/O) data lines 263. Data is read from the cells of memory array 242 by activating a word line 280 (via row decoder 244), which couples all of the memory cells corresponding to that word line to respective bit lines 260, which define the columns of the array. One or more bit lines 260 are also activated. When a particular word line 280 and bit lines 260 are activated, sense amplifier circuit 246 connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line 260 by measuring the potential difference between the activated bit line 260 and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
The memory cells of dynamic random access memories (DRAMs) include a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) cells which provides a substantial increase in component density. As component density has increased, cell capacitance has had to be decreased because of the need to maintain isolation between adjacent devices in the memory array. However, reduction in memory cell capacitance reduces the electrical signal output from the memory cells, making detection of the memory cell output signal more difficult. Thus, as the density of DRAM devices increases, it becomes more and more difficult to obtain reasonable storage capacity.
As DRAM devices are projected as operating in the gigabit range, the ability to form such a large number of storage capacitors requires smaller areas. However, this conflicts with the requirement for larger capacitance because capacitance is proportional to area. Moreover, the trend for reduction in power supply voltages results in stored charge reduction and leads to degradation of immunity to alpha particle induced soft errors, both of which lead to larger storage capacitance.
In order to meet the high density requirements of VLSI cells in DRAM cells, some manufacturers are utilizing DRAM memory cell designs based on non-planar capacitor structures, such as complicated stacked capacitor structures and deep trench capacitor structures. Although non-planar capacitor structures provide increased cell capacitance, such arrangements create other problems that effect performance of the memory cell. For example, with trench capacitors formed in a semiconductor substrate, the problem of trench-to-trench charge leakage caused by the parasitic transistor effect between adjacent trenches is enhanced. Moreover, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate which functions as one of the storage plates of the trench capacitor. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a soft error.
Another approach has been to provide DRAM cells having a dynamic gain. These memory cells are commonly referred to as gain cells. For example, U.S. Pat. No. 5,220,530 discloses a two-transistor gain-type dynamic random access memory cell. The memory cell includes two field-effect transistors, one of the transistors functioning as write transistor and the other transistor functioning as a data storage transistor. The storage transistor is capacitively coupled via an insulating layer to the word line to receive substrate biasing by capacitive coupling from the read word line. This gain cell arrangement requires a word line, a bit or data line, and a separate power supply line, which is a disadvantage, particularly in high density memory structures.
Recently a one transistor gain cell has been reported as shown in FIG. 3. (See generally, T. Ohsawa et al., “Memory design using one transistor gain cell on SOI,” IEEE Int. Solid State Circuits Conference, San Francisco, 2002, pp. 152-153). FIG. 3 illustrates a portion of a DRAM memory circuit containing two neighboring gain cells 301, 303. Each gain cell 301, 303 is separated from a substrate 305 by a buried oxide layer 307. Gain cells 301, 303 are formed on buried oxide 307 and have a floating body 309-1, 309-2, respectively, separating a source region 311 (shared for the two cells) and a drain region 313-1, 313-2, respectively. A bit/data line 315 is coupled to drain regions 313-1, 313-2 via bit contacts 317-1, 317-2, respectively. A ground source 319 is coupled to source region 311. Additionally, word lines or gates 321-1, 321-2 oppose the floating body regions 309-1, 309-2, respectively, and each is separated therefrom by a gate oxide 323-1, 323-2, respectively.
In the gain cell shown in FIG. 3, a back gate bias for each floating body 309-1, 309-2 is used to modulate the threshold voltage and consequently the conductivity of the NMOS transistor in each gain cell. The potential of floating body 309-1, 309-2 is made more positive by avalanche breakdown in drain regions, 313-1, 313-2, and collection of holes generated by floating body 309-1, 309-2. A more positive potential or forward bias applied to floating body 309-1, 309-2 decreases the threshold voltage and makes the transistor more conductive when addressed. Charge storage is accomplished by this additional charge stored on floating body 309-1, 309-2. Reset is accomplished by forward biasing the drain-body n-p junction diode to remove charge from floating body 309-1, 309-2.
However, avalanche breakdown is likely to result in damage to the semiconductor over a large number of cycles as required by DRAM operation, and high electric fields in the device will cause charge injection into the gate oxides or insulators. These factors can result in permanent damage and degradation of the memory cell.
There is a need for a memory cell structure adapted for high density design that provides a capability for higher reliability and longer operating life.